Semiconductor integrated circuits wafers, each comprising multiple chips, are produced by a plurality of processes in a wafer fabrication facility (fab). Each process step can introduce new defects, quality and reliability issues, failures, and yield losses. To improve manufacturing technologies and enhance chip (wafer) quality, reliability, and yield, the semiconductor wafers are measured, tested, monitored, and analyzed using a method such as failure mode analysis. The analysis includes a defect pattern recognition. However, current practices using defect pattern recognition rely on the creation of complex recognition rules or complicated models, resulting in low efficiency and effectiveness.